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MultiGEN TM GF9101 High Performance Multirate Digital Filter
DATA SHEET FEATURES * highly optimized & flexible architecture for multirate FIR filtering applications * implements dual 12 tap filters operating at 40 MHz or single 23 or 24 tap filter operating at 20 MHz maximum data rate * stores up to 108 fully-programmable 12 tap filters with 12 bit coefficients at each tap, dynamically addressable in each clock cycle * 3 flexible memory loading modes * 20 bit pipeline for cascading up to 3 devices * 20 bit output accumulator * filter output negate and zero controls * supports both symmetrical and asymmetrical FIR filters * 40 MHz maximum computation and input/output data rates APPLICATIONS Video rate conversion; High performance FIR filters; Adaptive digital filters; Video encoding; Digital modulation DESCRIPTION The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of signal processing functions using both symmetrical and asymmetrical filter structures. It is composed of a 12-tap FIR filter with internal RAM to hold up to 108 individual filters. An externally controlled address bus selects one of the 108 filters in each clock cycle. Pipelined architecture allows cascading of up to three devices with no additional hardware. Two 10-bit input shift registers are provided for multiplexed filtering applications. The 12-bit coefficients can be programmed in serial, high speed parallel or microprocessor modes. In the high speed parallel mode, any one of the 108 filters can be reprogrammed in 18 clock cycles. ORDERING INFORMATION
PART NUMBER GF9101 - CMQ PACKAGE 160 pin Metal Quad TEMPERATURE 0 to 70C
GF9101
1 +10 DATA-A-IN ENA +10 DATA-B-OUT ENB SEL-A/B ENC COEF-ADDR R 0 +10 DATA-A-OUT +10 TAP TAP R R R 7 R 7 CELL CELL 1 2 TAP CELL 11 TAP CELL 12
DATA-B-IN
14.11 ZERO R 4R 13.6 TRUNCATED NEGATE R DELAY 1,3,4,5 R 2 DATA B SEL
DELAY SEL 13.6
CONFIGURATION REGISTER
13.6 CARRY IN 13.6 PIPELINE-IN R 13.6 0 1 13.6
+
R
13.6
PIPELINE-OUT
FB-SEL
R
BLOCK DIAGRAM
Revision Date: July 1999 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 520 - 64 - 7
I/O DESCRIPTION
SYMBOL VDD PIN NO. 1, 10, 20, 29, 40, 41, 59, 69, 80, 81, 90, 99, 109, 120, 121, 129, 140, 150, 160 3, 6, 8, 19, 33, 36, 39, 46, 49, 60, 73, 76, 79, 83, 86, 88, 100, 113, 116, 119, 122, 125, 139, 153, 155, 159 138 I TYPE DESCRIPTION +5 V power supply pins. 0.1F capacitors between the VCC and GND pins are recommended.
GF9101
GND
Device ground.
CLK_IN
System clock. All inputs except for CONFIGURE, and all internal registers are clocked on the rising edge of CLK_IN. Input data to registers A0 - A11. 9 bit signed or 10 bit unsigned data. Input data to registers B11 - B0. 9 bit signed or 10 bit unsigned data. Shift enable for A0 - A11. Enables shifting of A registers when high. Shift enable for B0 - B11. Enables shifting of B registers when high. Enable for C0-C11. Enables C registers when high. The C registers transfer data from either the A or B registers depending on the state of SEL_A/B. Selects A or B registers. Selects registers A when high or registers B when low to be transferred to the C registers. Data bus for coefficients and configuration register: a) Parallel and microprocessor loading modes : COEF_DATA (7-0) is used to load 8 bit data into internal RAM. b) Serial Loading mode: COEF_DATA (7) is used to serially load the internal RAM. c) Configuration mode: COEF_DATA (6-0) are inputs to the CONFIGURATION register.
DATA_A_IN (9-0) DATA_B_IN (9-0) ENA ENB ENC
127, 128, 130-137 141-149, 151 23 24 25
I I I I I
SEL_A/B
22
I
COEF_DATA (7-0)
96-98, 101-105
I
COEF_ADDR (9-0)
78, 77, 75, 74, 72, 47, 45-42
I
Address bus for internal RAM (address 0 --> 107): a) Run mode: COEF_ADDR (6-0) selects one of the 108 sets of 12 coefficients in the internal RAM. b) Parallel and micro-processor loading modes: Selects the internal RAM address for the 8-bit data loading COEF_DATA (7-0).
COEF_WR
17
I
Enable for COEF_DATA (7-0). LOAD_EN must be enabled for COEF_WR to work: a) Parallel and micro-processor loading modes : Enables COEF_DATA (7-0) registers or loading 8 bit data in internal RAM. b) Serial Loading mode: On a high to low transition, a one bit data gets clocked in to the internal RAM through COEF_DATA bit 7.
LOAD_EN
18
I
Used during loading mode. This signal selects a particular GF9101 device when 2 or more share the same bus for loading. The particular GF9101 device is selected when set low. LOAD_EN must be enabled for COEF_WR. For a single GF9101 using the serial loading, this pin can be set low. This signal negates the filter sum before it enters the pipelined output section when high. Zeros filter sum before it enters the pipelined output section when low. Feedback select. Selects data in PIPELINE_IN when low or filter sum in PIPELINE_OUT when high to the input of the output accumulator.
NEGATE
126
I
ZERO FB_SEL
123 124
I I
2
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I/O DESCRIPTION
SYMBOL CONFIGURE PIN NO. 21 TYPE I DESCRIPTION GF9101 reset/configure. Resets the GF9101 when high for at least one clock period. Loads COEF_DATA (6-0) into the CONFIGURATION register on a high to low transition. This bit is set low in run mode. When CONFIGURE is high, the GF9101 is reset but the values in the internal RAM and registers in the run mode sections are not altered. This means that the GF9101 may be reconfigured after the internal RAM has been loaded. Pipeline input. Input to the output accumulator when FB_SEL is low.
GF9101
PIPELINE_IN (19-0)
38,37, 35, 34, 32-30, 28-26, 15-11, 9, 7, 5, 4, 2 71, 70, 68-61 58-50, 48 82, 84, 85, 87, 89, 9195, 106-108, 110112, 114, 115, 117, 118 16
I
DATA_A_OUT (9-0) DATA_B_OUT (9-0) PIPELINE_OUT (190)
O O O
Output data from register A11. Output data from register B0. Pipeline output. Output of the accumulator or PIPELINE_IN depending on FB_SEL.
S_LOAD_CMP
O
Serial loading complete. a) Serial loading mode: When high, indicates that all the internal RAM has been loaded.
SCAN_IN, SCAN_EN TEST POUT, SCANOUT
157, 156 158 152, 154
Set low. Set high. No Connect.
Note: All unused inputs of the GF9101 should be connected to GND
GF9101 OPERATION The GF9101 has two operating modes: the load mode and the run mode. In the load mode, the coefficients for the filters are written to the internal RAM. In the run mode, the GF9101 is used to filter signals. Before the GF9101 can filter signals, two steps must be performed: 1. CONFIGURATION - is accomplished by writing one 7 bit word into the CONFIGURATION REGISTER. This register holds static operating parameters that affect both the load mode and the run mode. 2. MEMORY LOADING - is done after configuration. The internal RAM must be loaded with at least one of the 108 filter coefficient sets before signals can be processed. CONFIGURATION The GF9101 is reset by holding CONFIGURE high for at least one clock cycle. Configuration occurs upon a high to low transition on the CONFIGURE pin. This transition registers COEF_DATA (6-0) into the CONFIGURATION REGISTER. Table 1 shows the meaning of each bit in the CONFIGURATION REGISTER.
When CONFIGURE is high, the GF9101 is reset but the values in the internal RAM and registers in the run mode sections are not altered. This means that the GF9101 may be reconfigured after the internal RAM has been loaded. MEMORY LOADING The GF9101 contains 12 tap cells with 108 12-bit memory locations for each tap. When loading the memory, the tap cells must be viewed as 6 memory banks with 108 24-bit memory locations in each bank. Each memory bank is assigned to a pair of tap cells as shown in Table 2. During configuration, either the parallel, microprocessor, or serial loading is selected. When in the load mode, the memory outputs are undefined. Please refer to the GF9101 block diagram and notice that, even though the memory outputs are undefined, several valid outputs may be in the processing section below the multipliers and can exit the GF9101 correctly. This would be useful for adaptive filtering where the tap memories can be changed while the GF9101 outputs are still valid. During power up, the internal RAM of the GF9101 is in a random state, and is not intialized to zero.
3
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TABLE 1: Configuration Register Format CONFIGURATION REGISTER BIT COEF_DATA(6-0) 0 1
PARALLEL LOADING
MEANING
MODE A (1 if A input signed, 0 if unsigned) MODE B (1 if B input signed, 0 if unsigned) DELAY_SEL selects delay for pipelining: Bits 3, 2 0, 0 0, 1 1, 0 1, 1 Delay in CLK_IN cycles 1 3 4 5
If parallel loading is selected, both the COEF_WR pin and the LOAD_EN pin determine whether the GF9101 is in the load mode. When COEF_WR and LOAD_EN are both low, the load mode is selected, the run mode is disabled, and writes to memory can occur. Parallel loading is random access and synchronous. Data is written through COEF_DATA (7-0) and its destination is determined by COEF_ADDR (9-0). Coefficient memory is loaded by writing 8 bits at a time, first to two temporary registers (bits 15 -0) and finally to the desired memory bank (bits 23-0). Each memory bank word is loaded in three clock cycles. COEF_ADDR (9-7) defines the address location for temporary registers (TEMP_REG_A and TEMP_REG_B) and memory banks. COEF_ADDR (6-0) determines the filter coefficient address (0 -107) in the internal RAM. COEF_ADDR (6-0) must be less than 108. In Table 3, COEF_ADDR (9-7) determines the following:
TABLE 3: Temporary Loading Registers and Memory Banks COEF_ADDR(9-7) (binary) 111 DESTINATION TEMP_REG_B TEMP_REG_A MB5 MB4 MB3 MB2 MB1 MB0
1
GF9101
3, 2
4
DATA_B_SEL 0 selects B12 for two 12 tap filters or one 24 tap filter by externally connecting DATA_A_OUT to DATA_B_IN. DATA_B_SEL 1 selects A12 for a 23 tap filter. LOAD MODE SELECT (see below) Bits 6, 5 0, 0 0, 1 1, 0 1, 1 Loading mode
6,5
NUMBER OF BITS 8 (15-8) 8 (7-0) 24 (23-0) 24 (23-0) 24 (23-0) 24 (23-0) 24 (23-0) 24 (23-0)
Serial 110 Parallel 101 Microprocessor Reserved 100 011
TABLE 2: Memory Locations for Internal RAM MEMORY BANKS (BITS) 0 (23-12) 0 (11-0) 1 (23-12) 1 (11-0) 2 (23-12) 2 (11-0) 3 (23-12) 3 (11-0) 4 (23-12) 4 (11-0) 5 (23-12) 5 (11-0) TAPS (BITS) 0 (11-0) 2 (11-0) 3 (11-0) 4 (11-0) 5 (11-0 6 (11-0) 7 (11-0) 8 (11-0) 9 (11-0) 10 (11-0) 11 (11-0) 12 (11-0)
010 001 000
NOTE 1: Memory Bank No. 5
TEMP_REG_A and TEMP_REG_B temporarily hold memory bits, (7-0) and (15-8) respectively. Three 8 bit writes are necessary to write one 24-bit memory as follows: 1. Load COEF_DATA (7-0) into TEMP_REG_A 2. Load COEF_DATA (7-0) into TEMP_REG_B 3. Load COEF_DATA (7-0), TEMP_REG_B (7-0), and TEMP_REG_A (7-0) into the selected memory bank, MB0MB5 (23-0). While COEF_ADDR (9-7) selects MB0-MB5 for writing, COEF_ADDR (6-0) selects the memory bank location that the 24-bit word is written into. Parallel loading is synchronous with CLK_IN. When COEF_WR and LOAD_EN are both low, 8-bit words will be written on the rising edge of CLK_IN. Consecutive writes may be done indefinitely by keeping COEF_WR and LOAD_EN low. A parallel loading timing diagram is shown in Figure 1.
4
520 - 64 - 7
The timing diagram shown in Figure 1 loads the memories shown in Table 4:
TABLE 4: Memory Loaded into Internal RAM in Parallel Load Mode TAP (location) 1 (0) 2 (0) 11 (107) 12 (107) 12-bit WORD IN HEX. FB2 EF4 CCC DDD MEMORY BANK MB0 MB0
GF9101
MB5 MB5
CONFIGURE
LOAD_EN
COEF_WR
COEF_DATA (7-0)
XX
F4
2E
FB
DD
CD
CC
XX
COEF_ADDR (9-0)
XX
300
380
000
36B
3EB
2EB
XX
CLK_IN
Fig. 1 Parallel Loading Timing Diagram
The address generated is shown in Table 5. Timing for the parallel loading signals is the same as that for other synchronous inputs.
TABLE 5: Address Generation for Parallel Loading Example DESTINATION TEMP_REG_A TEMP_REG_B MB0 TEMP_REG_A TEMP_REG_B MB5 COEF_ADDR (9-7) IN BINARY 110 111 000 110 111 101 COEF_ADDR (6-0) IN HEX X X 0 X X 6B COEF_ADDR (9-0) IN HEX 300 380 000 36B or 300 3EB or 380 2EB
MICROPROCESSOR LOADING If microprocessor loading is selected, the LOAD_EN pin alone determines the run mode or the load mode. When LOAD_EN is low, the load mode is selected, the run mode is disabled, but a write will not occur until COEF_WR is low. Microprocessor loading is random access and asynchronous. Like parallel loading, microprocessor loading uses COEF_DATA (7-0) and COEF_ADDR (9-0) to write three 8-bit words for each 24-bit memory written. Addressing is the same as for parallel loading. In microprocessor mode, at least one set of filter coefficients
5
520 - 64 - 7
need to be loaded into the internal RAM. If location 0 is used for filtering, MB0 > MB5 must be loaded for this location. The example shown in Figure 2 loads the value BBH into TEMP_REG_A.
LOAD_EN COEF-WR
SERIAL LOADING Serial loading is sequential and synchronous. If serial loading is selected the GF9101 will not enter the run mode until the entire serial load sequence is completed at which time the S_LOAD_CMP signal will go high. A bit will be written each time LOAD_EN is low and COEF_WR makes a high to low transition. Once the GF9101 is configured for serial loading, 24 x 108 x 6 =15552 bits must be written before the run mode is entered automatically. The 15552 bits must be entered in the order defined in Table 6. MB0 is loaded first from RAM location 0 starting to fill the first 12 bits of tap 2. MB5 RAM location 107, tap 11 is loaded last. When the serial load sequence is completed, S_LOAD_CMP will go high and the run mode will be active. Below is a serial loading timing diagram. This example shows the serial loading start-up sequence. Notice that the falling edge of COEF_WR is used to register the serial data. The frequency of COEF_WR should be 1/4 CLK_IN frequency.
GF9101
COEF_DATA (7-0) COEF_ADDR (9-0) 300H
BBH
Fig. 2 Microprocessor Loading Timing Diagram
TABLE 6: Serial Mode Loading Order
Memory Bank 0 Memory Bank 1 Memory Bank 5 Ram Location
1,2,3 .... 12 0,1,2 .... 11
13 ........ 24 0 .......... 11
2593 ............................. 2617 0 .......... 11 0 .......... 11
25 .................................. 48 0 .......... 11 .......... 0 .......... 11 ..........
2618 ............................. 2642 ............... 0 .......... 11 .......... 0 .......... 11 ..........
..........
..........
2568 ............................. 2592 0,1,2 .... 11 0 .......... 11
5160 ............................. 5184 ............... 0 .......... 11 0 .......... 11
15528 ...........................15552 0 .......... 11 0 .......... 11 107
CONFIGURE
LOAD_EN
COEF_WR
COEF_DATA (7)
BIT 1
BIT 2
BIT 3
BIT 15551
BIT 15552
CLK_IN
S_LOAD_CMP
Fig. 3 Serial Mode Timing Diagram
6
520 - 64 - 7
..........
...............
TAP 2
TAP 1
TAP4
TAP 3
TAP12
TAP 11
5185 ............................. 5208 0 .......... 11 0 .......... 11 0
5209 ............................. 5233 0 .......... 11 0 .......... 11 1
FILTER ARCHITECTURE For the following discussion on filter architecture, refer to the GF9101 Block Diagram and Figure 4.
+10.0
+10.0
DATA _A_IN
A REG
TO NEXT TAP
GF9101
ENA TO NEXT TAP ENB
R
B REG
+10.0
+10.0
DATA_B_IN
R
SEL-A/B
R
1
0
+10.0
C REG
ENC
R
+10.0 MODE A
CONFIGURATION REGISTER
0 1
MODE B
MULT MODE REG
SIGNED / UNSIGNED
+10.0 / 9.0 7
COEF-ADDR
R
108 x12 0.11 COEF REG
COEF REG
0.11
10.11
MULT REG
10.11
TO ADDER
Fig. 4 Tap Cell (1-12) COEFFICIENT MULTIPLICATION AND ADDITION STAGE
Two shift registers, A and B, are used to shift input data through the GF9101. Notice that if DATA_B_SEL was set low during configuration, data applied at DATA_A_IN enters at tap 1 and exits from tap 12, while data applied at DATA_B_IN enters at tap 12 and exits from tap 1. This gives two 12 tap filters. If DATA_B_SEL was set high during configuration, data applied at DATA_A_IN enters at tap 1, reverses direction at tap 12 (bypasses REG_12B) and exits from tap 1 on DATA_B_OUT, while DATA_B_IN is disabled. This gives a 23 tap filter. ENA and ENB control the shifting of the input data. The C register holds the next set of 12 input values to be applied to the multipliers. If ENC is high, SEL_A/B, determines whether the A or B shift register data enters the C register. SEL_A/B, also determines whether the MODE A or MODE B control signal enters the MULT_MODE register. The value in the MULT_MODE register determineswhether theinputdatato themultiplierisrecognized as signed or unsigned. MODE A and MODE B are separate, static control signals which determine signed/unsigned for A or B input data respectively. They are common to all taps. When using the GF9101 as a 23 or 24 tap filter (combiningREG_A and REG_B to get a single filter output), MODE A and MODE B should be in the same state. If not, a signed/unsigned 7
mismatch will occur. One needs to be cautious while using the GF9101 as two separate filters with MODE A and MODE B not in the same state (data entering REG_A is signed/ unsigned while in REG_B it is the opposite of REG_A) . If ENC is low and SEL_A/B, changes state, a signed/unsigned mismatch will occur. To avoid an error under these circumstances, always make ENC high after a SEL_A/B, state change. The input values in the C register are multiplied by the coefficient values in the COEF register and the result enters an adder tree . The coefficients that enter the COEF register are stored in the internal RAM and are selected by the externally controlled COEF_ADDR (6-0) bus, which is common to all taps. At the output of the adder tree is the untruncated sum of taps 1 through 12. This sum is then truncated as shown in the GF9101 Block diagram. The sum then passes through a variable delay along with the ZERO and NEGATE signals. The variable delay is provided so that complementary sums from cascaded GF9101's may be added together in the pipelined output stage. The ZERO signal zeros the sum and the NEGATE signal negates the sum.
520 - 64 - 7
PIPELINE_IN, PIPELINE_OUT STAGE
GF9101
The calculated filter sum from the adder tree and delay enters into the pipelined output stage. Figure 5 shows the block diagram for the pipelined structure. FB_SEL determines whether the sum is added to the current PIPELINE_OUT or the registered PIPELINE_IN. The result is then registered at PIPELINE_OUT. When using one GF9101, this configuration can be used to add two partial filter sums from the A and B registers. Another application would be to use the PIPELINE_IN port for adding DC offset or SYNC
and BURST signals (i.e. for 4:2:2 to 4SC rate conversion). This can be achieved by clocking in the SYNC and BURST signals from an external PROM connected to the PIPELINE_IN. By connecting PIPELINE_OUT of one GF9101 device to PIPELINE_IN of another, up to three GF9101's may be cascaded to form larger filters.
FILTER-SUM PIPELINE-IN 20 PROM R 20 0 1 20
+
20
R
PIPELINE-OUT
FB-SEL CLK-IN
R
GF9101
Fig. 5 Block Diagram for Pipelined Output Stage
CLK_IN
FILTER_SUM
XXX
SUM 1
SUM 2
XXX
SUM 3
XXX
PIPELINE_IN
003H
FB_SEL XXX PIPELINE_OUT SUM 1
SUM 1 + SUM 2
XXX
003H + SUM 3
XXX
Fig. 6 Timing Diagram for the Pipelined Output Stage
APPLICATION NOTES Video applications for the GF9101 include video rate conversion and high performance FIR filters. The following section presents a number of examples which show odd and even symmetric and asymmetric filters.
ODD-TAP SYMMETRIC FILTER
The GF9101 can be configured as an Odd-tap symmetric filter. A 23-tap odd-symmetric filter using one GF9101 will be discussed. For an odd-tap symmetric filter, the configuration word is shown in Table 7. The maximum data rate using this filter configuration is 20 MHz, where the filter is clocked at twice the data rate of 40 MHz, the frequency of CLK_IN. The filter has input data An and filter data coefficients Cn (C0 --> C11) as shown in Figure 7. The input enters the filter at DATA_A_IN and exits the filter from DATA_B_OUT. The coefficient C11 is only 8
520 - 64 - 7
multiplied by the data in reg. A_12 and reg.B_12 is bypassed. The data is shifted into the register by clocking ENA and ENB at the same time at half the CLK_IN frequency. The filter timing is shown in Figure 8.
TABLE 7: Configuration Word for an Odd-Tap Symmetric Filter BIT NO. 0 1 2 3 4 CONFIGURATION WORD 1 1 0 0 1 23-tap filter, bypass reg. B_12 Depending on loading mode. (See Table 1) DESCRIPTION Data A and B are both signed data2 One register delay
GF9101
5 6 NOTE:
X X
2: Bits 0 and 1 should have the same value for a 23 or 24 tap filter.
TABLE 8: Internal RAM Addresses and Contents COEF_ADDR (6-0) 00H MEMORY CONTENTS 12 coefficients, for tap 1--> tap 12
C11
C10
C10
C3 C2 C0 C4 C8
C9
C9 C3 C8 C4 C2 C0 (a) Filter Coefficients Cn C1
C1
C5 C6
C7
C7 C6
C5
A22 A23 A21 A17
A10 A16 A15 A11 A9 A5
A4 A3 (b) Input Data An
A25
A24
A20 A19
A18
A14 A13
A12
A8 A7
A6
A2 A1
A0
Fig. 7 Input Data An and Coefficients Cn
9
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DATA_A_IN
0
1
2
3
4
5
6
7
8
9
10
11
CLK_IN
ENA ENB SEL_A/B
B
A
B
A
B
A
B
A
B
A
B
A
GF9101
COEF_ADDR (6 - 0)
00H
ENC LOAD_EN ZERO CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 8 Timing Diagram for a 23-Tap Odd-Symmetric Filter
Assuming that the data A0 --> A21 has already been shifted into the filter registers, by clocking ENA and ENB the data A22 enters DATA_A_IN (Figure 9a). During the first CLK_IN rising edge, the data in the A registers (A22 --> A11) are selected by SEL_A/B , to be multiplied by the coefficients, C0 --> C11 in memory location 0, COEF_ADDR 00H . During the second CLK_IN rising edge the data in B registers (A0 --> A10) are selected by SEL_A/ B, to be multiplied by the coefficients, C0 -->C10 (Figure
9b). After passing through the adder tree and the delay (4 CLK_IN cycles in total), the two sums are added in the pipeline section of the filter. FB_SEL selects PIPELINE_IN during CLK_IN period 5, at which time a DC offset could be introduced at PIPELINE_IN to be added to the sum. During CLK_IN period 6, FB_SEL selects PIPELINE_OUT and the final filter sum is calculated and passed through to PIPELINE_OUT.
DATA-A-IN
A22
A21
A20
A12
A11
DATA-A-IN A22 DATA-B-OUT
A21 A0
A20 A1 A2
A12
A11 A10
DATA-B-OUT
A0
A1
A2
A10
C0
C0
x
C1
x
C2
x
C10
x
C11
x
x
C1
x
C2
x
C10
x
C11
x
PIPELINED ADDER
PIPELINED ADDER
(A22 x C0) + (A21 x C1) + (A20 x C2) +...+(A12 x C10) + (A11 x C11)
+
(A22 x C0) + (A21 x C1) + (A20 x C2) +...+(A12 x C10) + (A11 x C11)
(A0 x C0) + (A1 x C1) + (A2 x C2) +...+(A10 x C10)
Fig. 9a Data Flow Diagram for a 23 Tap Odd-Symmetric Filter EVEN-TAP SYMMETRIC FILTER
Fig. 9b Data Flow Diagram for a 23 Tap Odd-Symmetric Filter
The GF9101 can be configured as an even-tap symmetric filter. A 24-tap symmetric filter can be configured using one GF9101 by connecting the outputs of DATA_A_OUT to the inputs of DATA_B_IN and taking the output at 10
520 - 64 - 7
PIPELINE_OUT. For a 24-tap symmetric configuration word is shown in Table 9.
filter,
the
TABLE 9: Configuration Word for a 24-tap Symmetric Filter BIT NO. 0 1 2 3 4 CONFIG. WORD 1 1 0 0 0 24-tap filter, connect the outputs of DATA_A_OUT to the inputs of DATA_B_IN. Depending on the loading mode See Table 1 One register delay
3
DESCRIPTION Data A and B are both signed data
GF9101
5 6 NOTE
X X
3. Bits 0 and 1 should have the same value for a 23 or 24 tap filter
The filter coefficients are shown in Figure 10. The timing is verysimilar to that of the even-symmetric case.
C11 C 11 C10
C10
C9 C4 C0 C2 C6 C7 A17 A18 A19 A16 A15 C8 C3 C5
C9 C5
C4 C3 C0 C2
(a) Filter Coefficients Cn
C1
C8 C7 A7 A8 A9
C6
C1
A6 A5 (b) Input Data An
A24 A23 A22 A21
A20
A14 A13 A12 A11
A10
A4 A3 A2 A1
A0
Fig. 10 Input Data An and Coefficients Cn ASYMMETRIC FILTER TABLE 10:Internal RAM Address & Contents for a 24-tap Asymmetric Filter COEF_ADDR (6-0) 00H 01H MEMORY CONTENTS First set of 12 coefficients, C0 --> C11 Second set of 12 coefficients, C23 --> C12
The GF9101 can be used as a 24-tap asymmetric filter by configuring it the same way as the even-symmetric case. The difference is in the memory locations since the asymmetric case uses 24 different coefficients, i.e. two sets of filter coefficients. The filter coefficients and the memory locations are shown in Table 10. The timing diagram is shown in Figure 11. The data flow diagrams are shown in Figures 11a and 11b.
11
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DATA_A_IN
0
1
2
3
4
5
6
7
8
9
10
CLK_IN
GF9101
ENA ENB SEL_A/B
B
A
B
A
B
A
B
A
B
A
B
COEF_ADDR (6-0)
01H
00H
01H
00H
01H
00H
01H
00H
01H
00H
01H
ENC LOAD_EN
ZERO CONFIGURE
FB _SEL
PIPELINE _OUT
Fig. 11 Timing Diagram for a 24 Tap Asymmetric Filter
DATA-A-IN
DATA-A-IN A23 A22 A21 A13 A12
A23
A22
A21
A13
A12
DATA-B-OUT
DATA-B-OUT A0 A1 A2 A10 A11
A0
A1
A2
A10
A11
C0
x
C1
x
C2
x
C10
x
C11
x
C23
x
C22
x
C21
x
C13
x
C12
x
PIPELINED ADDER
PIPELINED ADDER
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
(A0 x C23) + (A1 x C22) + (A2 x C21) +...+(A10 x C13) + (A11 x C12)
+
(A23 x C0) + (A22 x C1) + (A21 x C2) +...+(A13 x C10) + (A12 x C11)
Fig. 11a Data Flow Diagram for a 24 Tap Asymmetric Filter
Fig. 11b Data Flow Diagram for a 24 Tap Asymmetric Filter
CASCADING In the previous section, configuration for a 24 tap filter using only one GF9101 was shown. To realize higher order (>24) filters, up to three GF9101's would allow a 72 tap FIR filter to be configured without any additional hardware. In Figure 13, two GF9101's are cascaded together to obtain a 48 tap filter. The data enters DATA_A_IN (device number 1) and exits from DATA_B_OUT (device number 1). In device number 2, the DATA_A_OUT bus is connected to DATA_B_IN in order to feed the data back in to the B12 12
520 - 64 - 7
register of the same device. The contents of the configuration register will be different for the two devices to compensate for a three register delay introduced when two GF9101's are cascaded to get a 48 tap filter. The configuration register contents are shown in Table 11.
For the 48 tap filter, input data A n and coefficients C n are shown in Figure 12. The pipelined output section of the 48 tap filter is shown in Figure 14. Note that two register delays are introduced due to R2 and R3 between the accumulators of device number 1 and number 2. An additional delay is
TABLE 11 Configuration Word for the Cascaded GF9101's DEVICE NO. 1 BIT NO. 0 1 2 3 4 CONFIG. WORD 1 1 0 0 0 DEVICE NO. 2 CONFIG. WORD 1 1 0 1 0
introduced when the filter-sum is fed back to be added to the next sum by selecting FB_SEL_1. The timing diagram for the 48 tap asymmetric filter is shown in Figure 15. The processing clock runs at twice the data rate since the A and B registers of the GF9101 are multiplexed internally..
GF9101
DESCRIPTION Data A and B are both signed data.
1 clock cycle delay in device no. 1 and 4 clock delay in device no. 2
Using each device as 2 x 12 tap filters. Note that in device no. 2 DATA_A_OUT is externally connected to DATA_B_IN. Assuming serial load mode selected for both devices.
5 6
0 0
0 0
C39 C6 C0 C1 C 2 C3 C5 C4 C7 C36 C37 C38 C40 C 41 C42 C47 C43 C44 C45 C46
A44 A45 A47 A46 A43 A42 A41 A11 A10
A9 A8 A7 A6
A40
A5 A4 A3 A1
A0
Fig. 12 Input Data An and Coefficients Cn
13
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GF9101
ZERO
NEGATE
FB_SEL-1
NEGATE
CLK_IN
SERIAL PROM
DATA COEFWR CONFIG CLK OE CE 7 6
CLK_IN +5V COEFWR CONFIG 1 2 3 4
FB_SEL-2
SERIAL PROM
DATA CLK OE CE 7 6
ZERO
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DATA_IN [9..0] ENA DB_IN9 DB_IN8 DB_IN7 DB_IN6 DB_IN5 DB_IN4 DB_IN3 DB_IN2 DB_IN1 DB_IN0 ENB SEL A/B SEL_A/B 22 SEL_A/B 141 142 143 144 145 146 147 149 151 151 58 57 56 55 54 53 52 51 50 48 24 DB_OUT9 DB_OUT8 DB_OUT7 DB_OUT6 DB_OUT5 DB_OUT4 DB_OUT3 DB_OUT2 DB_OUT1 DB_OUT0 ENB DB_IN9 DB_IN8 DB_IN7 DB_IN6 DB_IN5 DB_IN4 DB_IN3 DB_IN2 DB_IN1 DB_IN0 127 128 130 131 132 133 134 135 136 137 23 DA_IN9 DA_IN8 DA_IN7 DA_IN6 DA_IN5 DA_IN4 DA_IN3 DA_IN2 DA_IN1 DA_IN0 ENA DA_OUT9 DA_OUT8 DA_OUT7 DA_OUT6 DA_OUT5 DA_OUT4 DA_OUT3 DA_OUT2 DA_OUT1 DA_OUT0 ENA 141 142 143 144 145 146 147 149 151 151 DA_OUT9 DA_OUT8 DA_OUT7 DA_OUT6 DA_OUT5 DA_OUT4 DA_OUT3 DA_OUT2 DA_OUT1 DA_OUT0 DA_IN9 DA_IN8 DA_IN7 DA_IN6 DA_IN5 DA_IN4 DA_IN3 DA_IN2 DA_IN1 DA_IN0 ENA 71 70 68 67 66 65 64 63 62 61 127 128 130 131 132 133 134 135 136 137 23 71 70 68 67 66 65 64 63 62 61 ENB SEL A/B 22 58 57 56 55 54 53 52 51 50 48 24 DB_OUT9 DB_OUT8 DB_OUT7 DB_OUT6 DB_OUT5 DB_OUT4 DB_OUT3 DB_OUT2 DB_OUT1 DB_OUT0 ENB OFFSET [7..0] OUTPUT [11..0]
1 GF9101
2 GF9101
Fig. 13
14
+5V SLOADCMP 96 97 98 101 102 103 104 105 COEFD7 COEFD6 COEFD5 COEFD4 COEFD3 COEFD2 COEFD1 COEFD0 +5V CADR6 CADR5 CADR4 CADR3 CADR2 CADR1 CADR0 25 ENC C O CLK N F I G E N
18 17
38 37 35 34 32 31 30 28 27 26 15 14 13 12 11 9 7 5 4 2 PL_IN19 PL_IN18 PL_IN17 PL_IN16 PL_IN15 PL_IN14 PL_IN13 PL_IN12 PL_IN11 PL_IN10 PL_IN9 PL_IN8 PL_IN7 PL_IN6 PL_IN5 PL_IN4 PL_IN3 PL_IN2 PL_IN1 PL_IN0 PL_OUT19 PL_OUT18 PL_OUT17 PL_OUT16 PL_OUT15 PL_OUT14 PL_OUT13 PL_OUT12 PL_OUT11 PL_OUT10 PL_OUT9 PL_OUT8 PL_OUT7 PL_OUT6 PL_OUT5 PL_OUT4 PL_OUT3 PL_OUT2 PL_OUT1 PL_OUT0 96 97 98 101 102 103 104 105 COEFD7 COEFD6 COEFD5 COEFD4 COEFD3 COEFD2 COEFD1 COEFD0 82 84 85 87 89 91 92 93 94 95 106 107 108 110 111 112 114 115 117 118 PL_IN19 PL_IN18 PL_IN17 PL_IN16 PL_IN15 PL_IN14 PL_IN13 PL_IN12 PL_IN11 PL_IN10 PL_IN9 PL_IN8 PL_IN7 PL_IN6 PL_IN5 PL_IN4 PL_IN3 PL_IN2 PL_IN1 PL_IN0
38 37 35 34 32 31 30 28 27 26 15 14 13 12 11 9 7 5 4 2
PL_OUT19 PL_OUT18 PL_OUT17 PL_OUT16 PL_OUT15 PL_OUT14 PL_OUT13 PL_OUT12 PL_OUT11 PL_OUT10 PL_OUT9 PL_OUT8 PL_OUT7 PL_OUT6 PL_OUT5 PL_OUT4 PL_OUT3 PL_OUT2 PL_OUT1 PL_OUT0
82 84 85 87 89 91 92 93 94 95 106 107 108 110 111 112 114 115 117 118
SLOADCMP
ADDRESS [6..0]
78 77 75 74 72 47 45 44 43 42 COEF_AD9 COEF_AD8 COEF_AD7 COEF_AD6 COEF_AD5 COEF_AD4 COEF_AD3 COEF_AD2 COEF_AD1 COEF_AD0 F B S E L I N
158 157
ADDRESS [6..0]
CADR6 CADR5 CADR4 CADR3 CADR2 CADR1 CADR0
78 77 75 74 72 47 45 44 43 42 25 Z E R O 138
COEF_AD9 COEF_AD8 COEF_AD7 COEF_AD6 COEF_AD5 COEF_AD4 COEF_AD3 COEF_AD2 COEF_AD1 COEF_AD0 ENC F B E N W R T E S T N I N S E L
138 W R
L O A D T E S T N S C A N S C A N E N
156
C O E F
N E G A T E
126
N
124 123
C O CLK N F I G +5V
21
L O A D
C O E F
S C A N
S C A N E N
18 17 158 157 156
N E G A T E
126
Z E R O N
124 123
+5V
21
+5V
XC1736
XC1736
FILTER-SUM 1 20 OFFSET [7..0] R1 8 20 0 1
FILTER-SUM 2 20
20
R2 20
R3
20
0 1
20
20
R4
12 OUTPUT [11..0]
20 FB-SEL-1 R FB-SEL-2
R
GF9101
GF9101
DEVICE No.1
GF9101
DEVICE No.2
Fig. 14 Pipelined Output Stages for Two Cascaded GF9101's TABLE 12: Internal RAM Address and Contents for a 48-tap Asymmetric Filter using Two Cascaded GF9101's COEF_ADDR INTERNAL RAM CONTENTS Device No. 1 00H 01H C0 --> C11 (registers A1 --> A12) C47 --> C36 (registers B1 --> B12) Device No. 2 C12 --> C23 (registers A1 --> A12) C35 --> C24 (registers B1 --> B12)
Dedicated serial PROM's can be used to load the coefficients into the internal RAM of each GF9101. Note that when data is fed back into DATA_B_IN, it enters register B12 of device number 2. Therefore, while loading the coefficients into the internal RAM for the B registers the
coefficients should be arranged as shown in Table 12. If a single source is used for coefficient loading, the LOAD_EN signal is used to select the appropriate device. Also, the S_LOAD_CMP signal can be used as an indicator for a successful load.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK_IN
DATA_A_IN ENA ENB SEL_A/B COEF_ADDR (6-0)
00H
01H
00H
01H
00H
01H
00H
01H
00H
01H
00H
01H
00H
01H
LOAD_EN
ZERO
CONFIGURE
FB_SEL-1
FB_SEL-2 NEGATE
Fig. 15 Timing Diagram for a 48 Tap Asymmetric Filter
15
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127 128 130 131 132 133 134 135 136 137 23 141 142 143 144 145 146 147 148 149 151 24 22 38 37 35 34 32 31 30 28 27 26 15 14 13 12 11 9 7 5 4 2 96 97 98 101 102 103 104 105 78 77 75 74 72 47 45 44 43 42 25 138
DA-IN9 DA-IN8 DA-IN7 DA-IN6 DA-IN5 DA-IN4 DA-IN3 DA-IN2 DA-IN1 DA-IN0 ENA DB-IN9 DB-IN8 DB-IN7 DB-IN6 DB-IN5 DB-IN4 DB-IN3 DB-IN2 DB-IN1 DB-IN0 ENB SELAB PL-IN19 PL-IN18 PL-IN17 PL-IN16 PL-IN15 PL-IN14 PL-IN13 PL-IN12 PL-IN11 PL-IN10 PL-IN9 PL-IN8 PL-IN7 PL-IN6 PL-IN5 PL-IN4 PL-IN3 PL-IN2 PL-IN1 PL-IN0 COEF-D7 COEF-D6 COEF-D5 COEF-D4 COEF-D3 COEF-D2 COEF-D1 COEF-D0 COEF-AD9 COEF-AD8 COEF-AD7 COEF-AD6 COEF-AD5 COEF-AD4 COEF-AD3 COEF-AD2 COEF-AD1 COEF-AD0 ENC CLK_IN
GF9101 160 PIN Metal Quad
DA-OUT9 DA-OUT8 DA-OUT7 DA-OUT6 DA-OUT5 DA-OUT4 DA-OUT3 DA-OUT2 DA-OUT1 DA-OUT0 DB-OUT9 DB-OUT8 DB-OUT7 DB-OUT6 DB-OUT5 DB-OUT4 DB-OUT3 DB-OUT2 DB-OUT1 DB-OUT0 PL-OUT19 PL-OUT18 PL-OUT17 PL-OUT16 PL-OUT15 PL-OUT14 PL-OUT13 PL-OUT12 PL-OUT11 PL-OUT10 PL-OUT9 PL-OUT8 PL-OUT7 PL-OUT6 PL-OUT5 PL-OUT4 PL-OUT3 PL-OUT2 PL-OUT1 PL-OUT0 SLOADCMP
71 70 68 67 66 65 64 63 62 61 58 57 56 55 54 53 52 51 50 48 82 84 85 87 89 81 82 83 84 85 106 106 108 110 111 112 114 115 117 118 16
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Short Circuit Duration (single output) Storage Temp - 40 to +125 C VALUE -0.3 to +7.0 V -0.3 to (VDD +0.3) V 1 second
GF9101
RECOMMENDED OPERATING CONDITIONS
PARAMETER DC Supply Voltage Ambient Junction SYMBOL VDD TA TJ LIMIT + 3.0 to + 5.5 0 to +70 +150 UNIT V C C
+/- 5V 1, 10, 20, 29, 40, 41, 59, 69, 80, 81, 90, 99, 109, 120, 121, 129, 140, 150, 160
5 VCC= 5 V 4 P (W) TA = 25 C
GND 3, 6, 8, 19, 33, 36, 39, 46, 49, 60, 73, 76, 79, 83, 86, 88, 100, 113, 116, 119, 122, 125, 139, 153, 155, 159
3
2
1
10
20
30
40
50
60
70
80
Frequency (MHz)
GF9101 Power Consumption vs Clock Rate
21
18
17
158
157
156
126
124
123
GF9101 Pin Designations
VDD VDD
n SUBSTRATE n SUBSTRATE D1 p+ CONTROL INPUT n+ D2 n n p p D1 p+
n+ D2 p WELL GND GND
p WELL
Fig. 16 Equivalent Input/Output Circuit
16
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DC ELECTRICAL CHARACTERISTICS
VCC = 5V 5%, TA = 0C to 70C unless otherwise shown
PARAMETER Voltage Input LOW Voltage Input HIGH Voltage Output HIGH Switching Threshold Input Current Output Current HIGH
SYMBOL VIL VIH VOH VT IIN IOH IOH
CONDITIONS
MIN 3.5 2.4 -
TYP 4.5 2.5 +/-1 12 75 70 4.0 3.5
MAX 1.5 10 2 1 2 1 140 140 -
UNITS V V V V A mA mA mA mA mA mA mA pF pF
GF9101
VIN = VDD or VSS PIPELINE_OUT DATA_A_OUT, DATA_B_OUT PIPELINE_OUT DATA_A_OUT, DATA_B_OUT VIN = VDD or VSS VDD = Max, VO = VDD VDD = Max, VO = 0V
-10 30 25 -
Output Current LOW
IOL IOL
Quiescent Supply Current Output Short Circuit Current
IDD IOS
Input Capacitance Output Capacitance
CIN COUT
SWITCHING CHARACTERISTICS
VCC = 5V 5%, TA = 0C to 70C unless otherwise shown
Output Delay Setup Time Hold Time Clock Rate
tD tS tH MAX All Inputs All Inputs
2 6 -
8 -
40
ns ns ns MHz
17
520 - 64 - 7
GF9101 TIMING
T CLK-IN t1 t2
GF9101
CONFIGURE
t3
COEF-DATA (6-0)
t4
t5
Configuration Mode
DESCRIPTION 1 2 3 4 5 6 CLK_IN duration time (HIGH) CLK_IN duration time (LOW) CLK_IN period time CONFIGURE pulse width COEF_DATA to configure setup time COEF_DATA to configure hold time
SYMBOL t1 t2 T t3 t4 t5
MIN 12 12 25 T+10 10 5
MAX
UNIT ns ns ns ns ns ns
18
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LOAD_EN
COEF_WR
COEF_DATA (7-0)
t5
t6
GF9101
t7 COEF_ADDR (9-0)
t8
t3 t1 CLK_IN
t2
t4
Memory Loading - Parallel Interface
DESCRIPTION 1 2 3 4 5 6 7 8 LOAD_EN to CLK_IN set up time* LOAD_EN to CLK_IN hold time** COEF_WR to CLK_IN set up time* COEF_WR to CLK_IN hold time** COEF_DATA to CLK_IN set up time COEF_DATA to CLK_IN hold time COEF_ADDR to CLK_IN set up time COEF_ADDR to CLK_IN hold time
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8
MIN 4 6 4 6 2 6 2 6
MAX
UNIT ns ns ns ns ns ns ns ns
* to enable loading ** to disable loading
19
520 - 64 - 7
LOAD_EN t1 t2 t3
COEF_WR t5
t4
GF9101
COEF_DATA (7-0) t6 COEF_ADDR (9-0) t7 t8
Memory Loading - Microprocessor Interface
DESCRIPTION 1 2 3 4 5 6 7 8 LOAD_EN to COEF_WR set up time COEF_WR puls width low LOAD_EN to COEF_WR hold time COEF_WR pulse width, high COEF_DATA to COEF_WR set up time COEF_DATA to COEF_WR hold time COEF_ADDR to COEF_WR set up time COEF_ADDR to COEF_WR hold time
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8
MIN 2 80 6 20 10 10 2 6
MAX
UNIT na ns ns ns ns ns ns ns
20
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t1 LOAD_EN t3
t2
COEF_WR t4 t5
GF9101
COEF_DATA (7)
BIT 1
BIT 2
BIT 3
BIT 15551
BIT 15552
X
CLK_IN
S_LOAD_CMP
Memory Loading - Serial
DESCRIPTION 1 2 3 4 5 LOAD_EN to COEF_WR set up time LOAD_EN to COEF_WR hold time COEF_WR period COEF_DATA(7) to COEF_WR set up time COEF_DATA(7) to COEF_WR hold time
SYMBOL t1 t2 t3 t4 t5
MIN 4 6 4xT 2 6
MAX
UNIT ns ns ns ns ns
CLK_IN
t1
t2
EN A
t3 DATA_A_IN (9-0)
t4
DATA_A_OUT (9-0)
Run Mode
DESCRIPTION 1 2 3 4 ENA to CLK_IN set up time ENA to CLK_IN hold time DATA_A_IN to CLK_IN set up time DATA_A_IN to CLK_IN hold time
SYMBOL t1 t2 t3 t4
MIN 2 6 2 6
MAX
UNIT ns ns ns ns
21
520 - 64 - 7
CLK_IN
t1
SEL_A/B
GF9101
t2 ENC
t3
FB_SEL
t4
t5
Run Mode
DESCRIPTION 1 2 3 4 5 SEL_A/B to CLK_IN set up time ENC to CLK_IN set up time ENC to CLK_IN hold time FB_SEL to CLK_IN set up time FB_SEL to CLK_IN hold time
SYMBOL t1 t2 t3 t4 t5
MIN 2 2 6 2 6
MAX
UNIT ns ns ns ns ns
22
520 - 64 - 7
120 121
0.........................9 PIPELINE-OUT ZERO FB-SEL NEGATE 9 ................... 0 CLK-IN 9 ................... 9 ................... 0 DATA-B-OUT DATA-B-IN DATA-A-IN DATA-A-OUT 0..................7 COEF-DATA 10......................19 PIPELINE-OUT 9 COEF-ADDR 5 9 ................... 0 ........
81 80
GF9101
PIPELINE-IN 0.........................9
160 1
0 C O S C NS L 4 O FE O L COEF-ADDR E I A D C G- E E E F PIPELINE-IN 0 UANNNC W 10......................19 MER/ P NEBABCR
........
41 40
160 pin Metal Quad Pinout
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
REVISION NOTES: Remove `Not Recommended for New Designs' Watermark. Correct package name to 160 pin Metal Quad.
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright October 1998 Gennum Corporation. All rights reserved. Printed in Canada.
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